hanbit hm d2m32m4eag url: www.hbe.c o.kr hanbit electronics co.,ltd. rev. 1.0 (august.2002) 6 general description the hmd2m32m4eag is a 2 m x 32bit dynamic ram high - density memory module. the module consists of four cmos 1 m x 16 bit drams in 42 - pin soj packages mounted on a 72 - pin, double - sided, fr - 4 - printed circuit board. a 0.1 or 0.22uf decoupling capacitor is mounted on the printed circuit board for each dram components. the module is a single in - line memory module with edge connections and is intended for mounting in to 72 - pin edge connector sockets. all module components may be powered from a single 5v dc power supply and all inputs and outputs are ttl - compatible. features w part identification hmd2m32m4eag : 1024 cycles/32ms ref . gold w access times : 50, 60ns w high - density 8 mbyte design w single + 5v 0.5v power supply w jedec standard pinout w edo mode operation w ttl compatible inputs and outputs w fr4 - pcb design option s marking w timing 5 0 n s access - 5 0 6 0 n s access - 6 0 7 0 n s access - 7 0 w packages 72 - pin simm m performance range speed trac tcac trc 5 50ns 15ns 90ns 6 60ns 15ns 110ns 7 70ns 15ns 130ns p resence detect pins pin 50ns 60ns 70ns pd1 nc nc nc pd2 nc nc nc pd 3 vss nc vss pd4 vss nc nc pin symbol pin symbol pin symbol 1 vss 25 dq2 2 49 dq 8 2 dq0 26 dq7 50 dq2 4 3 dq1 6 27 dq2 3 51 dq 9 4 dq1 28 a7 52 dq2 5 5 dq1 7 29 a11 53 dq1 0 6 dq2 30 vcc 54 dq2 6 7 dq 18 31 a8 55 dq1 1 8 dq3 32 a9 56 dq 27 9 dq 19 33 /ras3 57 dq1 2 10 vcc 34 /ras2 58 dq 28 11 nc 35 nc 59 vcc 12 a0 36 nc 60 dq 29 13 a1 37 nc 61 dq1 3 14 a2 38 nc 62 dq 30 15 a3 39 vss 63 dq1 4 16 a4 40 /c as0 64 dq3 1 17 a5 41 /cas2 65 dq1 5 18 a6 42 /cas3 66 nc 19 a10 43 /cas1 67 pd1 20 dq4 44 /ras0 68 pd2 21 dq2 0 45 /ras1 69 pd3 22 dq5 46 nc 70 pd4 23 dq2 1 47 /w e 71 nc 24 dq6 48 nc 72 vss 8mbyte(2mx32) edo mode, 1k refresh 72pin simm, 5v design part no. hm d2m32m4eag pin assignment
hanbit hm d2m32m4eag url: www.hbe.c o.kr hanbit electronics co.,ltd. rev. 1.0 (august.2002) 7 ` functional block dia gram vc c vss 0.1 ? or 0.22 ? capacitor for each dram to all drams /ras0 /cas0 /cas1 /ras 2 /cas2 /cas3 /w e a0 - a11 /ras1 /cas0 /cas1 /ras 3 /cas2 /cas3 /ras /lcas /ucas /oe /w a0 - a11 u 2 /ras /lca s /ucas /oe /w a0 - a11 u 1 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 /ras lcas /ucas /oe /w a0 - a11 u 4 /ras /lcas /ucas /oe /w a0 - a11 u3 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq0 - 15 dq16 - 31 47 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
hanbit hm d2m32m4eag url: www.hbe.c o.kr hanbit electronics co.,ltd. rev. 1.0 (august.2002) 8 absolute maximum rat ings parameter symbol rating voltage on any pin relative to vss v in , out - 1v to 7.0v voltage on vcc supply relative to vss vcc - 1v to 7.0v power dissipation p d 4w storage temperature t stg - 55 o c to 150 o c short circuit output current i os 50ma w permanent device damage may occur if " absolute maximum ratings" are exceeded . functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended dc opera ting c onditions (voltage reference to v ss , t a =0 to 70 o c ) parameter symbol min typ max unit supply voltage vcc 4.5 5.0 5.5 v ground vss 0 0 0 v input high voltage v ih 2.4 - vcc+1 v input low voltage v il - 1.0 - 0.8 v dc and operating cha racteristics sym bol speed min max units i cc1 - 5 - 6 - - 305 284 ma ma i cc2 - 8 ma i cc3 - 5 - 6 - - 304 284 ma ma i cc4 - 5 - 6 - - 244 224 ma ma i cc5 - 4 ma i cc6 - 5 - 6 - - 304 284 ma ma i l(l) i o(l) - 20 - 10 20 10 m a m a v oh v ol 2.4 - - 0.4 v v i cc1 : operating cur rent * (/ras , /cas , address cycling @t rc =min.) i cc2 : standby current ( /ras=/cas=v ih ) i cc3 : /ras only refresh current * ( /cas=v ih , /ras, address cycling @t rc =min ) i cc4 : fast page mode current * (/ras=v il , /cas, address cycling @t pc =min ) i cc5 : st andby current (/ras=/cas=vcc - 0.2v ) i cc6 : /cas - before - /ras refresh current * (/ras and /cas cycling @t rc =min ) i il : input leakage current (any input 0v v in 6.5v, all other pins not under test = 0v) i ol : output leakage current (data out is disabled, 0v v out 5.5v v oh : output high voltage level (i oh = - 5ma ) v ol : output low voltage level (i ol = 4.2ma )
hanbit hm d2m32m4eag url: www.hbe.c o.kr hanbit electronics co.,ltd. rev. 1.0 (august.2002) 9 * note : i cc1 , i cc3 , i cc4 and i cc6 are dependent on output loading and cycle rates. specified values are obtained with the output open. i cc is specified as an average current. in i cc1 and i cc3 , address cad be changed maximum once while /ras=v il . in i cc4 , address can be changed maximum once within one page mode cycle. capacitance ( t a =25 o c, vcc = 5v, f = 1mz ) description symbol min max units input capacitance (a0 - a10) c in1 - 44 pf input capacitance (/w) c in2 - 48 pf input capacitance (/ras0) c in3 - 40 pf input capacitance (/cas0 - /cas3) c in4 - 29 pf input/output capacitance (dq0 - 31) c dq1 - 29 pf ac characteristics ( 0 o c t a 70 o c , vcc = 5v 10%, see notes 1,2.) - 5 - 6 standard operation symbol min max min max unit random read or write cycle time t rc 90 110 ns access time from /ras t rac 50 60 ns access time from /cas t cac 15 17 ns access time from column address t aa 25 30 ns /cas to output in low - z t clz 3 3 ns output buffer turn - off delay t off 3 13 3 15 ns transition time (rise and fall) t t 2 50 2 50 ns /ra s precharge time t rp 30 40 ns /ras pulse width t ras 50 10k 60 10k ns /ras hold time t rsh 13 17 ns /cas hold time t csh 40 50 ns /cas pulse width t cas 8 10k 1 0 10k ns /ras to /cas delay time t rcd 20 37 20 45 ns /ras to column address delay time t rad 15 25 15 30 ns /cas to /ras precharge time t crp 5 5 ns row address set - up time t asr 0 0 ns row address hold time t rah 10 10 ns column address set - up time t asc 0 0 ns column address hold time t cah 8 10 ns column address to /ras lead time t ral 25 30 ns read command set - up time t rcs 0 0 ns read command hold referenced to /cas t rch 0 0 ns
hanbit hm d2m32m4eag url: www.hbe.c o.kr hanbit electronics co.,ltd. rev. 1.0 (august.2002) 10 read command hold referenced to /ras t rrh 0 0 ns write command hold time t wch 10 10 ns write command pu lse width t wp 10 10 ns write command to /ras lead time t rwl 13 15 ns write command to /cas lead time t cwl 13 15 ns data - in set - up time t ds 0 0 ns data - in hold time t dh 8 10 ns refresh period 2k ref. t ref 16 16 ns write command set - up time t wcs 0 0 ns /cas setup time (c - b - r refresh) t csr 5 5 ns /cas hold time (c - b - r refresh) t chr 10 10 ns /ras precharge to /cas hold time t rpc 5 5 ns access time from /cas precharge t cpa 30 35 ns /cas precharge time (fast page) t cp 8 10 ns /ras pulse width (fast page ) t rasp 50 200k 60 200k ns /w to /ras precharge time (c - b - r refresh) t wrp 10 10 ns /w to /ras hold time (c - b - r refresh) t wrh 10 10 ns notes 1. an initial pause of 200 m s is required after power - up fo llowed by any 8 /ras - only or /cas - before - /ras refresh cycles before proper device operation is achieved. 2. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih(min) and v il(max) and are assumed to be 5ns for all inputs. 3. measured with a load equivalent to 2ttl loads and 100pf 4. operation within the t rcd(max) limit insures that t rac(max) can be met. t rcd(max) is specified as a reference point only. if t rcd is greater than the specified t rcd( max) limit, then access time is controlled exclusively by t cac . 5. assumes that t rcd 3 t rcd(max) 6. t ar , t wcr , t dhr are referenced to t rad(max) 7.this parameter defines the time at which the output achieves the open circuit condition and is not referenced to v oh or v ol . 8. t wcs , t rwd , t cwd and t awd are non restrictive operating parameter. they are included in the data sheet as electrical characteristic only. if t wcs 3 twcs(min) the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. 9. either t rch or t rrh must be satisfied for a read cycle. 10. these parameters are referenced to the /cas leading edge in early write cycles and to the /w leading edge in read - write cycles. 11. operation within the t rad(max) limit insures that t rac(max) can be met. t rad(max) is specified as a reference point only. if t rad is greater than the specified t rad(max) limit. then access time is controlled by t aa .
hanbit hm d2m32m4eag url: www.hbe.c o.kr hanbit electronics co.,ltd. rev. 1.0 (august.2002) 11 timing diagrams timing waveform of read cycle timing waveform of write cycle (early write) note : dout = open t rc v ih - v il - v ih - v il - v ih - v il - v ih - v il - v ih - v il - v oh - v ol - /ras /cas a /w /oe dq t ras t crp t rcd t csh t rsh t cas t rp t crp row address column address t asr t rah t rad t asc t cah t ral t rcs t rrh t rch t off t oez t aa t oea t clz t rac data - out open t cac t rc v ih - v il - v ih - v il - v ih - v il - v ih - v il - v ih - v il - v oh - v ol - /ras /cas a /w /oe dq0 t ras t crp t rcd t csh t rsh t cas t rp t crp row address colu mn address t asr t rah t rad t asc t cah t ral t cwl data - in t rwl t wcs t wch t wp t ds t dh
hanbit hm d2m32m4eag url: www.hbe.c o.kr hanbit electronics co.,ltd. rev. 1.0 (august.2002) 12 1.29 0.08 mm 0.25 mm max min 2.54 mm 1.27 mm gold : 1.04 0. 10 mm solder:0.914 0.10mm packaging informatio n 72pin - simm design (front view) o r dering information part number density org. package vcc speed hmd 2 m32m4 ea g - 5 8mbyte 2mx 32bit 72 pin - simm 5.0v 5 0ns hmd 2 m32m 4 ea g - 6 8mbyte 2mx 32bit 72 pin - simm 5.0v 6 0ns hmd 2 m32m 4 ea g - 7 8mbyte 2mx 32bit 72 pin - simm 5.0v 70ns 1.27 mm 3. 17 mm 1 107.95 m m 2.03 mm 1.02 mm 6.35 mm 95.25 mm 6.35 mm 3.18 mm dia 0.51 mm 101.19 mm 3.38 mm r 1.57 mm 19.05 mm 6.35 mm 10.16 mm
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